Senior ASIC Formal Verification Engineer
Listed on 2026-10-18
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Engineering
Test Engineer
Etched seeks a Formal Verification Engineer to advance verification across ASIC DV, interface IP, and SoC subsystems powering our ASICs. You will drive formal properties, enable proof convergence, and collaborate with architects, RTL designers, DV, emulation, software and firmware teams to prove design correctness and minimize corner-case bugs.
Expect to build reusable formal environments, employ System Verilog Assertions, and align verification with simulation and regression.
We are currently recruiting a Senior ASIC Formal Verification Engineer for our team in San Jose, CA, United States.
We have an opening for a Senior ASIC Formal Verification Engineer in San Jose, CA, United States within Engineering.
This role, Senior ASIC Formal Verification Engineer at US Health Partners, LLC, could be your next career step.
Are you ready to take on the Senior ASIC Formal Verification Engineer role at US Health Partners, LLC?
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