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Design Test Engineer

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Arrow Electronics, Inc.
Full Time position
Listed on 2026-10-18
Job specializations:
  • Engineering
    Electronics Engineer, Test Engineer, Hardware Engineer, Electronics Technician
Salary/Wage Range or Industry Benchmark: 112200 - 170500 USD Yearly USD 112200.00 170500.00 YEAR
Job Description & How to Apply Below
Position: Design for Test Engineer

Salary: $112, per year

Requirements
  • We look for 5 to 7 years of experience in design for test engineering.
  • We need hands-on expertise in scan insertion, ATPG, GLS, and pattern simulation with and without timing.
  • We expect experience with MBIST insertion and verification.
  • We require experience with IEEE 1149.1 JTAG insertion and validation.
  • We value scripting skills in Perl, Shell, and TCL.
  • We prefer experience working on multi-million-gate SoCs in networking, consumer, or related IPs such as PLL and Ser Des.
  • We use Mentor Tessent and look for familiarity with this toolset.
  • We seek candidates with a

    B.Tech or M.Tech in Microelectronics or Electronics.
  • We need strong communication skills.
  • We value knowledge of low-power DFT.
Responsibilities
  • We implement DFT for 3nm and 5nm networking chips, including IP-level DFT work.
  • We perform RTL checks for scan-insertion readiness using Synopsys Spyglass.
  • We carry out scan insertion with Tessent Test Kompress.
  • We generate ATPG patterns in compressed and uncompressed modes using tools such as Mentor Tessent, Cadence Modus, and Synopsys Tetramax.
  • We run pattern simulations both with and without timing across multiple corners using VCS.
  • We debug mismatches with Verdi.
  • We write scripts in Perl, Shell, and TCL to support automation and flow improvements.
  • We enhance DFT flows through DAeRT automation initiatives.
  • We improve Makefiles with extended scripts and targets to streamline the flow.
  • We perform MBIST insertion and verification at block and top levels.
  • We support silicon debug and bring-up for both block and top levels.
  • We insert and verify IEEE 1149.1 JTAG functionality.
Technologies
  • Flow
  • Support
  • Perl
  • Cloud
More

We are Arrow, through our eInfochips team, a leading global provider of product engineering and semiconductor design services with more than two decades of experience, over 500 products developed, and 40 million deployments across 140 countries. We partner with major technology companies and support connected product innovation for global clients. This is a full-time, fully on-site role in San Jose, California, with an annual hiring range of $112,200 to $170,500.

We offer competitive compensation and a strong benefits package that includes medical, dental, and vision insurance, 401(k) with matching contributions, short- and long-term disability coverage, HSA/HRA options, paid time off, tuition reimbursement, and growth opportunities.

last updated 41 week of 2026

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