Senior DFT Engineer – 3nm/5nm SoCs
Listed on 2026-10-18
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Engineering
Electronics Engineer, Test Engineer, Hardware Engineer, Systems Engineer
Arrow Electronics, Inc. in San Jose, CA seeks an experienced DFT Design Engineer to lead scan insertion, ATPG, MBIST and JTAG activities for 3nm and 5nm networking IPs. You will generate patterns, run timing-aware simulations, and debug with Verdi across SoCs. Strong scripting in Perl/Shell/TCL is required.
The role offers full-time on-site employment with competitive compensation and comprehensive benefits in a dynamic, global semiconductor services company.
We have an opening for a Senior DFT Engineer – 3nm/5nm SoCs in San Jose, CA, United States within Engineering.
This role, Senior DFT Engineer – 3nm/5nm SoCs at Arrow Electronics, Inc., could be your next career step.
Are you ready to take on the Senior DFT Engineer – 3nm/5nm SoCs role at Arrow Electronics, Inc.?
We would love to welcome a new Senior DFT Engineer – 3nm/5nm SoCs to our organisation in San Jose, CA, United States.
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