Senior Debug Verification Engineer; UVM/SoC)
Listed on 2026-10-18
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Engineering
Test Engineer, Hardware Engineer, Validation Engineer
Altera Corporation in San Jose, California, is seeking a Sr. Debug Design Verification Engineer to lead pre-silicon verification for SoC, FPGA and full-chip designs, and to develop test cases and UVM test benches.
The role requires defining verification strategies and coordinating with Design, SW and Architecture teams to achieve full coverage. Responsibilities include pre-silicon verification, testbench creation, and debugging architecture (JTAG, USB, PCIe).
Step into the Senior Debug Verification Engineer (UVM/SoC) role at Altera Corporation in San Jose, CA, United States and grow with us.
The advertised compensation is 149..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior Debug Verification Engineer (UVM/SoC) role in the description above.
We appreciate your interest in this position.
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