ASIC Design Engineer: RTL & Silicon BringUp On-site
Listed on 2026-10-19
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Engineering
Hardware Engineer, Electronics Engineer, Test Engineer, Systems Engineer
SiMa.ai, Inc. in San Jose, CA is seeking a Staff ASIC Design Engineer to own complex blocks from microarchitecture and RTL through verification and silicon bring-up.
This full-time, on-site role requires expert RTL (Verilog/System Verilog), strong block-level optimization, and collaboration with verification, physical design, architecture, and firmware teams to meet timing, power, and area targets. Salary ranges from $136,900 to $219,000.
The Staff ASIC Design Engineer: RTL & Silicon Bring Up On-site role , Inc. is now open for applications in San Jose, CA, United States.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Staff ASIC Design Engineer: RTL & Silicon Bring Up On-site role in the description above.
We appreciate your interest in this position.
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