Senior ASIC DFT and Memory Validation Engineer
Listed on 2026-10-19
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Engineering
Test Engineer
Cisco's Silicon One team in San Jose seeks an experienced engineer to lead test planning and DFT verification for next‑gen silicon. You will develop test benches and own MBIST methodology across the portfolio, collaborating with RTL and physical design teams to ensure high‑quality verification and scalable infrastructure.
Ideal candidates have 7+ years in test planning and deep familiarity with memory architectures and DFT tools (DVE/Verdi, Design Ware, Tessent).
Our organisation is growing, and we are hiring a Senior ASIC DFT and Memory Validation Engineer in San Jose, CA, United States.
For the Senior ASIC DFT and Memory Validation Engineer position at Cisco, we are reviewing applications now.
Step into the Senior ASIC DFT and Memory Validation Engineer role at Cisco in San Jose, CA, United States and grow with us.
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