Speed SerDes Synthesis & STA Engineer
Listed on 2026-10-20
-
Engineering
Electronics Engineer, Quality Engineering, Test Engineer
Astera Labs seeks a Synthesis & STA Engineer – High-Speed Ser Des in San Jose, CA. You will own logic synthesis, timing analysis, and sign-off for Ser Des IP, coordinating with analog, RTL, PD, and verification teams to ensure robust timing closures.
Deep expertise in SDC, Prime Time/Tempus, and 5nm/3nm nodes is required for successful chip integration. The role emphasizes end-to-end timing ownership, collaboration with IP vendors, and producing ECOs to meet aggressive clocking and data-path
We invite applications for the High-Speed Ser Des Synthesis & STA Engineer position located in San Jose, CA, United States.
Please review the full job details above before applying.
If your experience matches this role, we encourage you to apply.
All applications are reviewed carefully by our team.
The position is based in San Jose, CA, United States.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).