Senior AI Chip Verification Architect - PTO
Listed on 2026-10-20
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Engineering
Test Engineer, Hardware Engineer
Persimmons, Inc. is building AI hardware infrastructure and seeks a founding Senior ASIC Design Verification Engineer to own the verification of the AI Persimmons inference chiplet, coordinating with design, algorithm and compiler teams to ensure silicon aligns with specifications and is free of critical bugs before tape-out.
You will lead test plan development, build portable UVM test benches, drive coverage, validate C/C++ firmware on RISC-V cores, and extend verification with FPGA prototyping
Join us at Persimmons, Inc. as our next Senior AI Chip Verification Architect
- Flexible PTO in San Jose, CA, United States.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior AI Chip Verification Architect
- Flexible PTO role in the description above.
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