Senior Design Verification Engineer

Position: Senior Design Verification Engineer  United States of America
## Senior Design Verification Engineer San Jose, California, United States of America Apply Now Find out how well you match with this jobJob :
JR114836
** Our vision is to transform how the world uses information to enrich life for
* all*.
** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
** About the Role
** As a Senior Design Verification Engineer, you will develop and support the tools, automation, and flows used to design, verify, and tape out advanced memory products. You will work closely with design, layout, verification, and process teams to improve engineering productivity and design quality in one or more areas, including layout automation, physical verification, circuit simulation, and digital implementation.  ## Responsibilities
* Develop, enhance, and debug CAD tools, automation, and flows for custom IC design, layout, simulation, and verification.
* Contribute to one or more functional areas: layout automation, physical verification, circuit simulation, or digital implementation.
* Integrate, evaluate, and qualify in-house and commercial EDA tools in production environments.
* Partner with design, layout, verification, and process teams to resolve workflow and tool-integration challenges.
* Identify gaps in current tools and flows, and evaluate EDA industry offerings to improve quality, performance, and efficiency.
* Provide training, documentation, and production support to end users.
* Apply AI/ML and agentic AI to CAD automation, debugging, and user support.
* Develop clean, scalable software and mentor engineers to support their technical growth.
* Lead technical projects and contribute to CAD methodology roadmaps.  ##

Minimum Qualifications
* Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent.
* 5+ years of industry experience in CAD, EDA, or semiconductor design.
* Experience developing or supporting EDA tools and flows in at least one area: custom layout, physical verification, circuit simulation, or digital implementation.
* Experience with IC design CAD tools for schematic capture, layout, simulation, or verification.
* Proficiency in Python and at least one additional language, such as SKILL, Tcl, Perl, C, or C++, plus Linux/Unix and shell scripting.
* Solid CMOS and VLSI fundamentals, with clear communication and practical debugging skills across global teams.  ##

Preferred Qualifications
* Experience with Cadence Virtuoso and SKILL, including layout automation or parameterized cell (PCell) development.
* Experience with Calibre design rule checking (DRC) and layout versus schematic (LVS) flows, or rule-deck development in SVRF.
* Experience with circuit simulators such as Spectre, HSPICE, Fine Sim, Prime Sim, VCS, or Xcelium.
* Experience with RTL-to-GDS tools such as Fusion Compiler, Innovus, Prime Time, or Formality.
* Experience with parasitic extraction tools such as StarRC or Quantus.
* Experience applying AI/ML, large language models, or agentic AI to engineering workflows.
* Experience with source control, automated testing, and release management.
* Knowledge of DRAM, HBM, NAND, or emerging memory development.  
** What Sets This Role Apart
** This is not a traditional CAD role with AI as a secondary focus. AI is a core part of the mission. You will help define how AI is applied to real semiconductor design challenges while working closely with world-class design, process, and CAD teams. This role is especially well suited for a strong EDA/CAD engineer with practical AI experience who wants to grow into a broader AI design enablement role with…