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Senior Principal Design Engineer - Emulation & FPGA

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Cadence Design Systems
Full Time position
Listed on 2026-10-20
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Hardware Engineer, Test Engineer
Salary/Wage Range or Industry Benchmark: 154000 - 286000 USD Yearly USD 154000.00 286000.00 YEAR
Job Description & How to Apply Below

Cadence Design Systems in San Jose, CA, seeks a Senior Principal Design Engineer for Palladium & Protium Customer Support. You will work directly with leading semiconductor and systems companies to deploy Cadence hardware emulation and FPGA prototyping, bridging customers with AE, PE, and R&D teams to deliver advanced verification solutions.

Responsibilities include enabling customers, defining emulation requirements, driving FW/FPGA system solutions, debugging across hardware and software, and

This role, Senior Principal Design Engineer
- Emulation & FPGA at Cadence Design Systems, could be your next career step.

We have an opening for a Senior Principal Design Engineer
- Emulation & FPGA in San Jose, CA, United States within Engineering.

This role, Senior Principal Design Engineer
- Emulation & FPGA at Cadence Design Systems, could be your next move.

Are you ready to take on the Senior Principal Design Engineer
- Emulation & FPGA role at Cadence Design Systems?

Position Requirements
10+ Years work experience
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