Senior DFT Design Engineer ‑Gen ICs

Altera Corporation in San Jose, CA, is seeking a Senior DFT Design Engineer to define DFT architectures and implement test logic for FPGA, processors, DSP, SERDES, IO, and multi-die designs. You will perform ATPG pattern generation and pre-silicon validation to ensure manufacturability and quality.

You will collaborate with IP and integration teams to align DFT features with timing and functionality, and work with test development to support silicon bring-up, debug, and production readiness.

We have an opening for a Senior DFT Design Engineer for Next‑Gen ICs in San Jose, CA, United States within Engineering.

If your experience matches this role, we encourage you to apply.

All applications are reviewed carefully by our team.

The position is based in San Jose, CA, United States.

This opportunity is part of our work in Engineering.