ASIC DFT/DV Verification Lead - Hybrid
Listed on 2026-10-20
-
Engineering
Test Engineer, Hardware Engineer
Cisco's Silicon One team in San Jose seeks a DFT Verification Lead to drive test planning and develop robust test benches for comprehensive DFT validation across silicon stages. You will collaborate with Front-end RTL and backend PD teams to ensure high-quality test coverage.
The role requires strong System Verilog, DVE/Verdi debugging, and TCL/Python/Perl scripting skills, with a focus on scalable DFT solutions for new silicon devices.
The ASIC DFT/DV Verification Lead
- Hybrid (San Jose) position in the Engineering field is open for applications.
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This posting is for the ASIC DFT/DV Verification Lead
- Hybrid (San Jose) role at Cisco, based in San Jose, CA, United States.
We are looking to fill the ASIC DFT/DV Verification Lead
- Hybrid (San Jose) position at Cisco in San Jose, CA, United States.
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