Formal Verification Engineer

Chip Agents is revolutionizing chip design and verification with agentic-AI workflows. Founded by experts in AI and semiconductor design, we partner with top-10 semiconductor companies, hyperscale cloud providers, and cutting-edge startups. Our platform accelerates RTL development, functional verification, and simulation—unlocking new levels of productivity and design quality.

We are seeking a highly capable Formal Verification Engineer to join our core product and research team. You will work closely with our AI engineering, research, and EDA teams to build advanced agentic AI systems for semiconductor verification.

Your expertise in formal methods, testplan development, property specification, assertion-based verification, and proof debugging will help shape how AI systems reason about complex hardware behavior. You will play a central role in teaching our AI agents how verification engineers identify key design behaviors, write properties, manage complexity, analyze counterexamples, close proof convergence gaps, and validate RTL with mathematical rigor.

This is a unique opportunity to apply deep formal verification expertise at the frontier of AI-assisted chip design

• Identify key design behaviors and translate them into clear formal verification testplans for sophisticated designs.
• Develop, refine, and debug System Verilog Assertions, formal properties, environment assumptions, constraints, and cover properties.
• Build abstraction models to overcome complexity challenges and achieve full proofs, or bounded proofs with sufficient coverage.
• Drive formal tools for best performance, including tuning engines, proof strategies, and run configurations to improve convergence.
• Use formal verification tools to analyze RTL, prove design correctness, and debug counterexamples to identify the root causes of failures.
• Collaborate with AI engineers and researchers to model and codify formal verification workflows.
• Create reusable formal verification examples, design patterns, proof strategies, and edge cases to train and evaluate AI agents.
• Help AI systems interpret design specifications, generate properties, reason about RTL behavior, and debug counterexamples.
• Support benchmarking and evaluation of AI-assisted formal verification productivity across realistic IP and SoC verification tasks.
• Contribute to flow and script development that improves verification efficiency for the team and for our AI workflows.
• Clearly communicate formal verification coverage and results to customers, partners, and internal stakeholders.
• Work closely with customers, product, and research teams to translate formal verification pain points into automated AI workflows.
• Contribute to methodology development for assertion-based verification, formal apps, equivalence checking, connectivity checking, and coverage closure.

• Strong expertise in formal verification methodologies and signoff flows.
• Hands-on experience with Jasper Gold, VC Formal, Questa Formal, or equivalent tools.
• Deep knowledge of System Verilog Assertions (SVA) and assertion-based verification.
• Experience writing formal testplans and implementing them with assumptions, assertions, and cover properties.
• Experience proving complex properties, building abstraction models, debugging counterexamples, and achieving formal closure.
• Familiarity with SAT/SMT-based reasoning and formal verification fundamentals.
• Experience with CDC, RDC, lint, and static verification methodologies.
• Strong RTL design and microarchitecture understanding, with the ability to debug RTL to find failure causes.
• Experience verifying production IPs, subsystems, or SoCs.
• Proficiency in Python, Tcl, or scripting for verification automation.
• Strong communication skills, including the ability to explain formal coverage and results to partners and non-specialists.
• Interest in applying AI/LLMs to hardware design and verification workflows.

• Work at the frontier of AI and semiconductor design.
• Collaborate with a world-class team spanning AI, systems, and EDA.
• Shape a foundational shift in how chips are built.

• $150K/yr – $350K/yr + Offers Equity. We are open to discuss above-scale compensation with exceptional candidates on a case-by-case basis.
• Unlimited PTO and full benefits (medical, vision, dental, 401k).
• Two engineering-centric offices with free parking, private gym, and free lunch, drinks and snacks.