ASIC STA Technical Lead

The application window is expected to close on: 01/11/2027

Meet the Team The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.

Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact You will be in the Silicon One development organization as an ASIC DFT STA Technical Lead.  You are a detail-oriented STA engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity.  You will collaborate with cross-functional teams, communicate complex timing data clearly.  As a member of this team, you will also be involved in crafting groundbreaking next generation networking chips.

You will help lead to drive the DFT and quality process through the entire implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

Minimum Qualifications Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience

Prior working experience with RTL design, CDC/RDC and conformal verification, SDC development.

Prior working experience in timing constraint development and verification.

Prior programming experience with at least 2 or more of the following scripting languages:
Perl, TCL, Python, or Makefile.

Preferred Qualifications Masters degree + 15+ years experience.

Prior working experience in debugging and analyzing PCIE timing constraints, TSMC memory timing constraints.

Prior working experience with RTL design, CDC/RDC and conformal verification.

Prior working experience in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST.Prior working experience with SDC debugging & STA tools like Synopsys TCM/Primetime.

Prior working experience with synthesis tools:
Synopsys Fusion/design Compiler.

Prior working experience with Tessent tool like DFT insertion in RTL.Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $ to $ and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full…