DIC Memory DTCO Engineer

We are building the memory subsystems for next-generation data center-class ASICs — large-scale, multi-reticle, chiplet-based 3D designs purpose-built for AI/ML training and inference, cloud compute, and networking infrastructure. We are looking for a 3

DIC Memory DTCO Engineer to design and qualify high-bandwidth SRAM and embedded memory IP for these heterogeneous, multi-die 3

DIC products. You will own memory macro design, physical implementation, and characterization for memories that must deliver high bandwidth and operate correctly across chiplets built on different process nodes, reticle-stitched or stacked and bonded together (hybrid bonding, TSV, or 2.5D/3D packaging), and connected through high-bandwidth die-to-die interfaces. This is a hands-on circuit and physical design role at the intersection of custom memory design, physical design/optimization, DTCO, cross-die timing signoff, and advanced packaging/3

DIC co-design for data center-scale silicon.

• Architect high-bandwidth embedded memory for multi-reticle, chiplet-based 3
  
  DIC systems — balancing die-to-die latency, bandwidth, power delivery, and thermal constraints across heterogeneous dies in data center accelerator and networking SoCs.
• Own physical design and optimization for memory-heavy blocks: floor planning, macro placement/tiling, power grid design, IR-drop/EM mitigation, and timing/congestion closure, including across reticle boundaries.
• Plan power distribution across multiple power rails/voltage domains, define custom routing plans for memory and mixed-signal blocks, and drive TSV planning (placement, density, pitch, keep-out zones) with floor planning, PDN, and package teams.
• Drive DTCO with process/technology teams — tuning bitcell architecture, track height, contacted poly pitch, and metal stack choices against PPA and yield for memory-heavy, data center-scale dies.
• Own cross-die timing signoff across the 3D stack-up: STA through TSVs/hybrid-bonding interconnect, setup/hold margining across die and reticle boundaries, closing timing under PVT, OCV/AOCV, and clock-skew variation.
• Apply low-power techniques — voltage scaling, retention modes, power gating, near-threshold operation — for memories spanning chiplets with different power domains and data center power/thermal envelopes.
• Run signal/power integrity analysis for high-bandwidth memory interfaces crossing die boundaries: IR drop, noise coupling, cross-die timing closure.
• Develop and validate DFT/MBIST/repair schemes for embedded memories, supporting test and yield recovery in stacked-die, multi-reticle environments.
• Drive silicon characterization, correlation, and debug of memory test chips and first-silicon bring-up; feed yield/reliability and bandwidth data (retention, SER, aging) back into design and DTCO decisions.
• Collaborate cross-functionally with process/TCAD, packaging, physical design, timing signoff, DFT, and firmware teams across the product lifecycle.
• Help evolve internal memory compiler/IP flows, PDKs, and 3
  
  DIC-aware design methodologies for multi-reticle, chiplet-based platforms.

• Required Qualifications
• BS/MS/PhD in EE, CE, or related field; 5+ years (or equivalent depth at senior/staff level) of hands‑on custom circuit/memory design experience.
• Experience designing high-bandwidth SRAM sense amps and periphery circuits at advanced process nodes (3nm and below preferred).
• Transistor-level analog/mixed-signal design skills using SPICE-class simulators (HSPICE, Spectre, Fine Sim) for characterization, Monte Carlo, and corner analysis.
• Physical design and optimization experience (floor planning, P&R, clock tree, IR-drop/EM analysis) for memory-heavy blocks, resolving congestion, timing, and power trade-offs…