Senior ASIC Design Verification Engineer

The application window is expected to close on: 11/19/2026

Meet the Team The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.

Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco’s revolutionary data center solutions. You will define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms, contribute to a multi-disciplined engineering teams to meet the power, performance, and area goals for products. You will:

Drive the definition, architecture, and design of high-performance ASICs while owning complex or multiple functional areas.

Define new verification methodologies to support advanced design architectures and develop re-usable code for future projects.

Lead design verification effort by solving block-level issues and participate in cluster and chip-level issue resolution, and drive reviews to recognize areas of architectural concerns.

Architect, develop, and maintain cluster and top-level Design Verification (DV) environment infrastructure.

Build DV environments from scratch for cluster and chip levels.

Develop, implement, and enhance test plans and tests for cluster and chip verification, using both constraint-random and directed stimulus.

Ensure comprehensive verification coverage through code and functional coverage implementation and review.

Qualify RTL design by running Gate Level Simulations with timing annotation on netlists.

Support design testing in emulation environments.

Debug issues at ASIC, SW and Systems levels and help in lab bring-up and post silicon validation.

Minimum Qualifications Bachelors degree in Computer, Electrical or Electronics Engineering, + 7 years of relevant technical experience, or Masters degree + 4 years of relevant technical experience with a focus on ASIC design and verification.

Experience in OOP concepts, System Verilog or UVM methodology.

Experience leading verification teams or assignments projects.

Experience with scripting using Perl and/or Python.

Preferred Qualifications

Experience with forwarding logic, parsers, or P4.Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS.Knowledge of formal verification tools (e.g., IEV or VC Formal).Domain knowledge in one or more protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP.Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.

We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you. Message to applicants applying to work in…