Principal IC Package Design Engineer

Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakthrough data transport and acceleration technology is ushering in a new era of connectivity and capabilities in the vehicle and at the edge, including highly reliable autonomy, over-the-air servicing and AI-backed applications.

Ethernovia's co-founders are serial technology entrepreneurs with multiple prior successful ventures together. We are well-funded and backed by some of the worlds’ leading technology investors, having secured $154M ($90+M Series-B and $64M Series-A) in total funding to date:

• (financial backers include:
  Porsche SE, Qualcomm, AMD, Western Digital, Maverick Silicon, Socratic Partners, Conduit Capital, and CDIB-TEN Capital)

Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025.

With talented employees on 4 continents, we have filed 50+ patents to date.

Join Ethernovia’s team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive cutting edge designs from concept to silicon to the future of mobility.

Principal IC Package Design Engineer

Summary:

We are seeking a visionary and deeply technical

Principal IC Package Design Engineer to lead the architecture, design, and execution of advanced packaging solutions for our next-generation Ethernet switches and PHYs
. You will be responsible for the entire package lifecycle—from early-stage feasibility and architectural definition to detailed layout, signal/power integrity (SI/PI) co-design, thermal management, and mass production release.

This role requires a blend of deep technical expertise in advanced packaging technologies (e.g.,
Flip-Chip BGA
, high-density substrates) and the leadership capability to collaborate across Silicon Design, Systems/PCB, Reliability, and external OSAT vendors.

• Package Architecture & Feasibility:Lead the definition of package concepts, substrate stack-ups, bump/ball maps, and pinouts to optimize for system cost, electrical performance, and thermal constraints.
• Detailed Package Design:Execute complex, high-speed, multi-layer package layouts (
  FCBGA, FCCSP
  , SiP) utilizing industry-standard EDA tools.
• SI/PI & Thermal Co-Design:Partner closely with Signal/Power Integrity and Thermal engineers to ensure package designs meet stringent targets for high-speed Ser Des (56G/112G+), power delivery networks (PDN), and thermal dissipation.
• Substrate Design Integration:Define design rules and manage substrate layout, routing optimization, and manufacturing constraints (DFM/DFA).
• OSAT & Vendor Management:Drive technical engagements with leading substrate suppliers and OSATs. Evaluate vendor capabilities, negotiate design rules, and resolve manufacturing/assembly issues during NPI (New Product Introduction) and production ramp.
• Cross-Functional Collaboration:Act as the bridge between Silicon IC Design and System/PCB teams to ensure seamless chip-package-board co-design and optimization.
• Technology
  
  Roadmap:
  
  Stay at the forefront of semiconductor packaging trends (e.g., advanced organic substrates, glass substrates, co-packaged optics) to influence Ethernovia’s long-term hardware roadmap.