RTL​/Digital Design Engineer

Develop clean, efficient RTL for IPs and subsystems and carry designs through lint, CDC and synthesis.

ASIC Design San Jose, CA / Austin, TX (USA)

This role focuses on hands-on RTL development for IP blocks and subsystems. You will work from micro-architecture specifications, write and optimise Verilog/System Verilog, and ensure that designs are structurally clean, timing-friendly and ready for verification, DFT insertion and synthesis.

• Write and optimise RTL for datapath and control logic.
• Create block-level micro-architecture documents and interface specifications.
• Run Lint, CDC and RDC and resolve all violations.
• Perform preliminary synthesis to evaluate timing and area.
• Support verification engineers with design walkthroughs and debug.
• Participate in design reviews and maintain design documentation.

• Bachelor's in Electrical/Computer Engineering (Master's preferred).
• Good grasp of FSMs, pipelining, arbitration, FIFOs and asynchronous interfaces.
• Experience with simulation and lint tools.
• Working knowledge of synthesis and static timing concepts.
• Scripting ability in Python or Tcl.

• Exposure to processor, DMA, memory controller or interconnect design.
• Experience with FPGA prototyping of RTL.
• Familiarity with low-power design techniques.

You'll work on production silicon for the industry's leading semiconductor companies, in a small team where your contribution is visible and your growth is a priority. We offer competitive compensation, flexible engagement models and continuous upskilling.