Synthesis & STA Engineer
Listed on 2026-10-29
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Engineering
Electronics Engineer, Hardware Engineer
Own synthesis, constraints and static timing signoff from RTL through post-route across all corners and modes.
Physical Design San Jose, CA / Austin, TX (USA)
You will develop timing constraints, run logic synthesis with PPA optimisation, and lead static timing analysis and signoff for blocks and full-chip. The role is central to predictable timing closure and requires close coordination with RTL, PD and DFT teams.
What you'll do- Develop and validate SDC constraints for functional and test modes.
- Run RTL-to-gate synthesis with Design Compiler/Genus and optimise PPA.
- Perform multi-corner, multi-mode STA using Prime Time or Tempus.
- Analyse and fix timing violations; drive timing ECOs with PD.
- Run formal equivalence (Conformal/Formality) and constraint checks.
- Perform signoff timing including SI, OCV/AOCV/POCV and IR-aware analysis.
- Bachelor's or Master's in Electrical Engineering.
- Strong hands-on experience with synthesis and STA tools.
- Deep understanding of timing concepts: clocks, exceptions, CDC, derates and variation.
- Experience writing and debugging SDC constraints for complex SoCs.
- Experience with at least two tape-outs.
- Experience with hierarchical timing (ETM/ILM) methodologies.
- Low-power synthesis with UPF.
- Physical-aware synthesis and DFT-aware synthesis.
Intech
You'll work on production silicon for the industry's leading semiconductor companies, in a small team where your contribution is visible and your growth is a priority. We offer competitive compensation, flexible engagement models and continuous upskilling.
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