Design Verification Engineer

Own verification of IP, subsystem and SoC-level designs using UVM and coverage-driven methodologies for our semiconductor partners.

As a Design Verification Engineer at I2

Intech you will build and maintain System Verilog/UVM environments that give our partners first-pass silicon confidence. You will work with architects and RTL designers to define verification strategy, develop reusable testbench components, and drive coverage closure on complex IP and SoC designs.

• Develop verification plans from architecture and micro-architecture specifications.
• Build and maintain UVM test benches, sequences, scoreboards and reference models.
• Drive functional and code coverage closure; write System Verilog assertions.
• Debug RTL and testbench failures and work with designers to root-cause issues.
• Run gate-level simulations and power-aware (UPF) simulations where applicable.
• Maintain regression infrastructure and triage nightly results.

• Bachelor's or Master's in Electrical/Computer Engineering or related field.
• Strong hands-on experience with System Verilog and UVM.
• Solid understanding of digital design, bus protocols (AMBA AXI/AHB/APB) and clocking.
• Experience with industry simulators (VCS, Xcelium or Questa) and coverage tools.
• Scripting ability in Python, Perl or Tcl for automation.
• Excellent debugging and communication skills.

• Formal verification experience (Jasper Gold, VC Formal).
• Exposure to PCIe, DDR, USB, Ethernet or other high-speed protocols.
• Emulation or FPGA prototyping experience (Palladium, Zebu, Veloce).

You'll work on production silicon for the industry's leading semiconductor companies, in a small team where your contribution is visible and your growth is a priority. We offer competitive compensation, flexible engagement models and continuous upskilling.