ASIC Design Engineer

Design and integrate digital blocks and subsystems from specification through synthesis-ready, DFT-ready RTL.

ASIC Design San Jose, CA / Austin, TX (USA)

You will translate architectural requirements into robust, synthesizable RTL and integrate IPs into subsystem and SoC-level designs. The role spans micro-architecture definition, RTL coding, lint/CDC/RDC cleanliness, low‑power intent, and close collaboration with verification, DFT and physical design teams through tape‑out.

• Define micro‑architecture and write detailed design specifications.
• Develop high‑quality, synthesizable RTL in System Verilog/Verilog.
• Integrate in‑house and third‑party IPs; manage SoC interconnect and memory maps.
• Run and clean Lint, CDC and RDC checks; author UPF for low‑power designs.
• Support synthesis, timing closure and ECO activities.
• Collaborate with DV, DFT and PD teams to deliver tape‑out ready designs.

• Bachelor's or Master's in Electrical/Computer Engineering.
• Proven RTL design experience on ASIC or SoC projects.
• Strong understanding of digital design fundamentals, timing and clock domain crossing.
• Familiarity with Lint/CDC tools (Spy Glass, Questa CDC) and synthesis flows.
• Experience with bus protocols such as AXI, AHB, APB.
• Scripting in Python, Perl or Tcl.

• Experience with low‑power design (UPF/CPF) and multi‑voltage domains.
• IP‑XACT based integration flows.
• Exposure to high‑speed interfaces or processor subsystems.

You'll work on production silicon for the industry's leading semiconductor companies, in a small team where your contribution is visible and your growth is a priority. We offer competitive compensation, flexible engagement models and continuous upskilling.