Lead ASIC Physical Design Engineer

Lead block and full-chip physical implementation from netlist to GDSII on advanced technology nodes.

Physical Design San Jose, CA / Austin, TX (USA)

As a Lead Physical Design Engineer you will own the implementation methodology for complex blocks and top-level integration, mentor a team of PD engineers, and be the primary technical interface with our partners' design and signoff teams. You will drive predictable timing closure on high-speed designs and ensure tape-out schedules are met.

• Own floor planning, power planning, placement, CTS, routing and timing closure for blocks and top level.
• Define and maintain the implementation flow and methodology across the team.
• Drive PPA optimisation and closure of timing, power, IR/EM and physical verification (DRC/LVS/ANT).
• Mentor and review the work of PD engineers; plan and track deliverables.
• Interface with RTL, DFT, STA and signoff teams to resolve cross-functional issues.
• Lead ECO implementation and final tape-out checks.

• Bachelor's or Master's in Electrical Engineering with 10+ years in physical design.
• Multiple tape-outs at 16nm or below;
  FinFET experience strongly preferred.
• Expert in Innovus or Fusion Compiler/ICC2, Prime Time/Tempus, Calibre and Redhawk/Voltus.
• Deep understanding of CTS, low-power implementation and hierarchical design.
• Strong Tcl/Python scripting and flow automation skills.
• Demonstrated technical leadership and partner-facing communication.

• Experience with chiplet or multi-die implementation.
• Exposure to high-performance CPU/GPU or networking datapaths.
• Familiarity with design-for-manufacturability and yield optimisation.

You'll work on production silicon for the industry's leading semiconductor companies, in a small team where your contribution is visible and your growth is a priority. We offer competitive compensation, flexible engagement models and continuous upskilling.