Senior ASIC Physical Design Engineering Technical Lead

The application window is expected to close on: 11/30/2026

Meet the Team
the Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production is within our team, we’re able to think differently, experiment more, and work quickly.

Join us to power the future of the digital world.

• RTL-to-GDSII implementation, including Logic Synthesis, Hierarchical Floor planning, Place and Route, Static Timing Analysis, Power Integrity, and Equivalence checks with a focus on Performance and Die-Size Optimization.
• Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
• Work closely with RTL, DFT, Implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology.
• Guide Clock Tree Synthesis (CTS) strategies and provide actionable feedback to the implementation teams.
• Execute STA setup, convergence methodologies, and sign-off processes across multi-mode, multi-corner scenarios.
• Complete Functional and Timing ECO implementation using industry-standard flows and contribute to automation for STA methodology.
• Evaluate multiple timing methodologies/tools across different technologies and design types.

• Bachelor’s Degree in Electrical Engineering with 12+ years of Physical Design experience or Master’s Degree in Electrical Engineering with 8+ years of Physical Design experience, or PhD in Electrical Engineering with 5+ years of Physical Design experience.
• Experience working on Fullchip activities.
• Experience with RTL2
  
  GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies.
• Experience working with EDA tools like Innovus, Primetime/Tempus, Redhawk/Voltus and Calibre.

• Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis.
• Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
• Experience in Fullchip floor-planning and power grid planning.
• Experience with custom clock (H‑Tree or Mesh) at chip level.
• Experience with Python, TCL, or Perl programming.

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

The starting salary range posted for this position is $ to $ and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market…