Senior ASIC Design Engineer – DSP​/Analog​/SerDes

Celero Communications, a dynamic semiconductor startup, is seeking a Senior ASIC Design Engineer to develop advanced ASICs for high-speed optical communication systems. The role involves designing high-performance digital circuits and collaborating with cross-functional teams to integrate DSP, Analog, and Ser Des technologies.

• Design and implement high-performance digital circuits and ASIC blocks using Verilog and System Verilog.
• Develop and integrate DSP, digital communication, and high-speed Ser Des functionality into complex ASIC designs.
• Collaborate with Analog, Ser Des, DSP, Architecture, Verification, Physical Design, and Systems teams to develop mixed-signal ASICs.
• Participate in the design and development of high-speed data paths, signal processing blocks, control logic, and interfaces for optical communication systems.
• Perform synthesis, timing analysis, lint, formal equivalence, and Clock Domain Crossing (CDC) activities.
• Optimize designs for performance, power, and area (PPA).
• Conduct RTL simulation and debugging to ensure design functionality and performance.
• Contribute to block-level and top-level integration, verification, and silicon bring-up.
• Participate in architecture and design reviews and provide technical guidance to other engineers.
• Develop scripts and automation using Python, Tcl, or similar languages to improve design and verification efficiency.

• Master's or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.
• 10 years of experience in digital ASIC design, with ownership of complex ASIC blocks or subsystems.
• Strong proficiency in Verilog and/or System Verilog.
• Understanding of digital design principles, RTL design, and ASIC development methodologies.
• Hands-on experience with ASIC design flows and industry-standard EDA tools.

• Strong knowledge of Digital Signal Processing (DSP), High-speed Ser Des, Analog/Mixed-Signal ICs, Digital communications, and Optical communications.
• Experience with DSP algorithms, data-path architectures, FEC, equalization, modulation/demodulation, or high-speed communication technologies.
• Understanding of Ser Des architectures and high-speed interfaces, including TX/RX datapaths and related mixed-signal interfaces.
• Experience with synthesis, static timing analysis, Lint, CDC, formal verification, and RTL simulation.
• Familiarity with verification methodologies such as UVM and/or formal verification.