ASIC​/RTL Design Engineer

Fully onsite in San Jose CA

You will build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX analog front ends, calibration loops) in System Verilog. Those models drop into a System Verilog UVM verification environment used for high-speed Ser Des and SoC IP. You will work closely with analog circuit designers, RTL designers and verification engineers. Successful candidates will be responsible for leading, and participating in, the modeling and verification of leading-edge designs in advanced CMOS processes.

• Reading schematics, netlists and circuit specifications to define what each model must capture
• Developing model architecture and accuracy targets, balancing fidelity against simulation speed
• Writing behavioral System Verilog models of analog blocks
• Validating models against transistor-level simulation results
• Debugging simulation failures and finding the root cause in the model, RTL or testbench
• Documenting model behavior, limitations and interfaces

Hands-on experience writing behavioral models of analog circuits in System Verilog. Working knowledge of analog and mixed-signal circuit fundamentals and of the System Verilog UVM methodology, with proven skill debugging failures in simulation and waveforms. Familiarity with high-speed interface standards is a plus.

• Looking for a candidate with RTL coding experience but also Analog Design/Modeling experience.
• Would like to see experience with VCS and LTSPICE and HSPICE simulation.

VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status