Sr. Design Engineer

Position: Sr. Staff Design Engineer
# Join the FPGA Leader## Sr. Staff Design Engineer Apply:
San Jose, CA:
Posted Yesterday:
End Date:
November 30, 2026 (29 days left to apply):
R-103659#
** Lattice Overview
** There is energy here...energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry.

Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.
*
* Job Description:

**** Duties:
** Responsible for RTL design and verification, leveraging deep expertise in Lattice Semiconductor products and customer applications across diverse market segments.  This role involves:
* Developing complex systems from concept to board-level validation using Lattice proprietary FPGA architectures and tool flows.
* Building embedded systems within Lattice FPGAs, including microprocessor design and embedded software development.
* Integrating IPs into FPGA software flows and supporting end-to-end system implementation.
* Analyzing hardware capabilities and contributing to customer solution strategies.
* Architecting Soft IPs with detailed technical specifications and coordinating development efforts.
* Collaborating cross-functionally with software and applications teams to communicate requirements, resolve issues, and drive enhancements.

Specific duties include:
* Architect and develop DDR Memory Controller soft IPs
* Optimize soft IPs to achieve better performance (latency, size, frequency)
* FPGA design and implementation using software primitives
* Integration with third-party hardened PHYs
* Team leadership and stakeholder management
* Static Timing Analysis (STA) and constraint writing
* RISC-V based system design and evaluation
* Customer support and issue resolution
* Quality review of third-party deliverables
* Test development to validate implementation and ensure high quality
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* Minimum Requirements:

*** Bachelor’s degree in Electronics Engineering, Applied Physics or related field
* 8 years of experience as Design Engineer or related field

Prior experience to include:  
* FPGA and SoC ASIC development.
* IP for FPGA and ASIC products
* FPGA RTL design, logic verification, debug and timing closure
* DDR protocols (e.g.: DDR3, DDR4, LPDDR4, DDR5)
* High-speed interface subsystems
* High-speed protocols (PCIe, Ethernet, and MIPI)
* Peripheral IPs (UART, SPI, I2C, and I3C)
* Hardware validation and hardware interoperability testing
** Pay & Benefits
** Consistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role.

Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work…