Physical Design Engineer - ASIC Products Division; APD

Location:

San Jose, CA Position Type:
Full-Time

Broadcom’s ASIC Products Division (APD) is the global leader in custom high-performance silicon solutions. We partner with the world’s most innovative technology companies—spanning hyper-scale cloud providers, AI pioneers, and tier-1 networking infrastructure leaders to co-design and manufacture complex, custom ASICs that power the modern digital backbone.

The Physical Design team within APD is the world-class execution engine behind the industry's most advanced custom silicon. We push the limits of silicon technology by combining deep architectural expertise, advanced IP, cutting-edge physical design methodologies in 3nm/2nm/A14 nodes, and advanced 2.5D/3D chiplet integration to solve the most demanding compute and bandwidth challenges.

We transform ultra-complex architectures into fully realized, high-yielding, first-pass silicon success.

• Pioneering First-Pass Silicon in 3nm/2nm:
  Our team consistently pushes the boundary of physics, taking the largest and most complex die sizes from floorplan to tapeout on leading-edge foundry nodes (N7, N5, N3, and N2).
• Record-Breaking Scale & Complexity:
  We regularly execute full-chip physical implementation for ultra-large-scale ASICs exceeding tens of billions of transistors, multi-gigahertz clock frequencies, and dense multi-die 2.5D/3D integration (CoWoS, HBM3/4, chiplet architectures).
• Methodology & Flow Leadership:
  We develop and maintain cutting-edge in-house (AI Driven) automation and methodology across different EDA tools, setting the benchmark for signoff quality and turn-around-time (TAT).

Broadcom’s ASIC Products Division (APD) is looking for a motivated Physical Design Engineer (NCG) to join our Physical Design team. In this role, you will work alongside experienced engineers in executing the implementation tasks for next-generation high-performance networking, AI/ML accelerators, and custom cloud ASICs. In this role, you will gain hands-on experience in complex block-level floor planning, synthesis, Place and Route (P&R), clock tree synthesis (CTS), timing closure, and signoff across cutting-edge deep sub-micron nodes (N5/N3/N2/A14).

• Participate in block-level floor planning, and run placement and route (P&R) flows using industry-standard EDA tools.
• Perform Static Timing Analysis (STA), debug timing paths, and execute ECOs for timing closure.
• Run Physical Verification checks (DRC, LVS, ERC, Antenna) and resolve signoff violations.
• Analyze IR drop and electromigration (EM) to ensure power grid integrity.
• Develop and maintain automated scripts (TCL, Python, Ruby) to enhance flow efficiency and productivity

• Education:
  
  Bachelor's Degree in Electrical Engineering, Computer Engineering + 2yrs of experience or Master’s degree in Electrical Engineering, Computer Engineering (Graduation date within the past 12 months).
• Solid understanding of digital CMOS logic design, standard cell libraries, and semiconductor fundamentals.
• Familiarity with static timing analysis (STA) concepts, clocking, and setup/hold timing.
• Hands-on coursework, lab experience, or academic projects using EDA design tools (Cadence Innovus/Tempus, Synopsys IC Compiler II/Prime Time, or Siemens tools).
• Proficient in scripting languages such as TCL, Python, Ruby, or Bash.

• Prior internship or research experience in ASIC physical design, synthesis, or physical verification.
• Basic understanding of Design for Testability (DFT), low-power intent (UPF/CPF), and FinFET technologies.
• Excellent problem-solving, debugging, and analytical skills.

• Legal…