NAND Custom Test Circuit Design Engineer

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a NAND Custom Test Circuit Design Engineer, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction!

• Develop, integrate, and optimize custom test circuit architectures for NAND flash memory designs, including transistor-level digital, analog, mixed-signal, monitoring, control, and memory-array interface circuits.
• Interpret product specifications and test requirements; define circuit functionality, interfaces, operating limits, cont rollability, observability, and validation criteria.
• Create, review, and optimize schematics, device sizing, bias structures, sensing and monitoring paths, multiplexers relevant to test circuits.
• Analyze circuit testability and robustness to ensure compliance with quality, coverage, manufacturability, power, area, and reliability requirements.
• Drive Design for Test (DFT) requirements for custom NAND test circuits, including cont rollability and observability, test-mode architecture, fault coverage, built-in self-test and diagnostic access where applicable, and ATPG or pattern-generation interfaces; partner with Product Engineering and test teams to close coverage gaps and enable efficient wafer and package testing.
• Apply Design for Manufacturing (DFM) principles to improve process-window margin, yield, and high-volume manufacturability through PVT and Monte Carlo analysis, mismatch and variation assessment, layout-aware design rules, redundancy or repair considerations, and silicon-data-driven optimization.
• Validate custom test circuits using XA simulations, Verilog simulations, and mixed-signal validation environments.
• Collaborate closely with layout teams on matching, parasitic sensitivity, shielding, routing, guard rings, device placement, and layout-dependent effects; review post-layout results and drive closure.
• Evaluate circuit risks including leakage, contention, floating nodes, device overstress, power sequencing, current density, EM/IR, and long-duration stress conditions.
• Create and debug test sequences and test modes required to control, observe, characterize, and validate custom test circuits at wafer and package levels.
• Work with Product Engineering during first-silicon bring-up, debug and characterization, failure isolation, simulation-to-silicon correlation, and ramp to high-volume production.
• Use laboratory measurements and silicon data to identify root cause and recommend circuit, test-mode, characterization, or screening improvements.
• Apply a Design + AI approach as a core responsibility by using AI-assisted and agentic engineering workflows to accelerate circuit review, simulation triage, waveform analysis, root-cause investigation, automation, documentation, and knowledge retrieval while maintaining engineering rigor and sign-off subject area.
• Develop Python or scripting-based automation and AI-enabled solutions that improve design quality, reduce turnaround time, and increase engineering efficiency.
• Document test-circuit methodologies, specifications, design decisions, validation results, silicon correlation, and clear technical recommendations.

• Bachelor's or Master's degree in Electrical…