R&D Engineer Ic Design

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The Network Switch Group at Broadcom has brought some of the most complex and cutting edge networking ASIC's and multi-chip solutions to market. The group develops ASIC's for L2/L3 switching and routing for various market segments. These products support the latest networking protocols and features as well as manage extremely large volumes of traffic in the order of tens of Terabits/sec.

These networking ASIC's support a large number of ports and port speeds ranging from tens of Mb/s to hundreds of Gb/s as well as various line interfaces and protocols..

You will be responsible for the micro-architecture, design, RTL coding, debugging and synthesis of complex functional blocks in the Traffic Manager / Memory Management Unit used in Broadcom’s market leading network switch products.

Responsibilities include:

• High quality micro-architecture and design specifications

• Verilog RTL coding and synthesis

• Testplan reviews, assertions, debugging, code and functional coverage

• Floor plan, timing, congestion resolution with Physical Design team

• Post silicon bring-up, debug, failure analysis.

BS + 12+ years of related experience or MS + 10+ years of relevant experience

Compensation and Benefits

The annual base salary range for this position is $141,300- $226,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package:
Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

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