Principal Software Engineer - Low Power Verification
Listed on 2026-01-03
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Software Development
Software Engineer, C++ Developer
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Principal Software Engineer — Low-Power Verification (Palladium & Protium)We are seeking a highly skilled Senior Software Engineer to help build the next generation of low‑power verification software for the Palladium and Protium emulation platforms. In this role, you will drive innovations that improve the debuggability, performance, and scalability of multi‑billion‑gate UPF (Unified Power Format) designs across modular compilation flows (2‑state and 4‑state).
Key Responsibilities- Design, develop, and optimize low‑power verification software for Palladium and Protium.
- Improve UPF design debuggability within the IXCOM Modular Compiler and Parallel Partition Compiler (2‑state and 4‑state).
- Enhance compiled streaming probes and accelerate waveform generation for large‑scale designs.
- Collaborate closely with R&D, Product Engineering (PE), and Application Engineering (AE) to deploy UPF solutions across diverse flows, including:
- AVIP + UPF + 2/4‑state
- UVMA + UPF + 2/4‑state
- MC + UPF
- Dielets + UPF
- Consolidate and unify UPF software across Palladium and Protium platforms.
- Contribute to major initiatives such as:
- MC + PPC flow with UPF 4‑state
- UPF compilation time optimization
- Full Vision UPF probe integration
- SAGE UPF debug with Verisium
- Bachelor’s degree in Computer Science or Electrical Engineering with 7+ years of relevant experience, or a Master’s degree with 5+ years, or a PhD with 1+ year of industry experience.
- Strong proficiency in object‑oriented design and C++ development.
- Experience with standard C/C++ libraries and the C++ STL.
- Demonstrated ability to build high‑performance software for large‑scale data processing.
- Scripting experience in Perl, Tcl/Tk, and/or Python.
- Familiarity with IEEE 1801 and UPF implementation.
- Experience with Verilog, System Verilog, and VHDL.
The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Our benefits programs include paid vacation and paid holidays, a 401(k) plan with employer match, an employee stock purchase plan, a variety of medical, dental, and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
Equal Employment Opportunity PolicyCadence is committed to equal employment opportunity throughout all levels of the organization. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Cadence participates in the E‑Verify program in certain U.S. locations as required by law.
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