Intern, Power-Thermal Simulation Software Engineer

San Jose, California, United States

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• Project Overview:
  Physical memory is a bottleneck for AI systems; power and heat decide how fast AI models can run. Our lab is building a simulator tool to aid memory architecture and packaging teams in their work, allowing them to visualize how their designs impact power consumption and heat generation quickly without needing a physical prototype and hours of computation. As a software intern, you will gain an understanding of the entire data pipeline as you develop this tool, improving its features or user experience.
• Skills You’ll Learn:
  • Simulation Infrastructure
  • User Interface Development
  • Power & Thermal Engine Development

Samsung’s Power & Thermal Lab is seeking a software engineering intern to contribute in the development of our power and thermal simulation tool.

We are a small, fast‑moving team where direct ownership and minimal busywork empower every member to tackle the same real‑world problems. Working with authentic data, real partners, and production‑grade results, our contributions flow straight into platforms used across the company.

As an intern, you will support research and product teams across multiple projects, including providing end‑to‑end simulation, regression testing, and data‑pipeline management. You will work on real projects with tangible results, receive mentorship, and help shape the scope of work in a collaborative environment where hardware, software, and thermal experts work side‑by‑side on next‑generation AI memory technologies.

Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy

SVP, R&D (Power & Thermal Lab)

• Build automation pipelines for simulation runs, regression testing, and result tracking.
• Implement and optimize a trace‑driven power‑thermal simulation engines.
• Generate transient power maps, perform spatiotemporal hotspot analysis, and interface with reduced‑order/CFD‑calibrated thermal solvers.
• Develop high-fidelity, advanced RTL
  - SystemC-, and C-based power macromodels for AI memory component IPs using analytical modeling, LUT, FSM, NN, and their hybrid.
• Extract activity-, value-, and state-dependent power features from C/SystemC/RTL simulations.
• Define power-relevant functional states (transaction/state-based abstraction).
• Calibrate models using synthesis‑assisted anchors and validate against RTL/gate‑level and silicon data.
• Manage time‑indexed simulation flow across power and thermal domains.
• Complete other responsibilities as assigned.

• Pursuing Masters or PhD in Computer Science, Electrical and Computer Engineering, or related major.
• Must have at least 1 academic quarter/semester remaining
• C++, scripting workflows in Python or Bash, SystemC and/or transaction-level modeling.
• RTL design, synthesis and analysis research and/or experience (Verilog/System Verilog/SystemC), preferred
• Experience with…