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Senior RTL Verification Engineer - SystemVerilog​/UVM Expert

Job in San Marcos, Hays County, Texas, 78667, USA
Listing for: Mogi I/O : OTT/Podcast/Short Video Apps for you
Full Time position
Listed on 2026-01-28
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Engineering Design & Technologists, Test Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 USD Yearly USD 80000.00 100000.00 YEAR
Job Description & How to Apply Below
A technology company is seeking a Verification Engineer to lead RTL design verification for high-speed digital systems. Responsibilities include developing verification plans, building verification environments, and ensuring functional coverage. Candidates should have over 5 years of digital/RTL engineering experience and at least 3 years in design verification, with strong knowledge of VLSI flows and hands-on experience in System Verilog and UVM.

This role offers a competitive salary in an innovative environment.
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Position Requirements
10+ Years work experience
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