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Senior RTL Verification Engineer – SystemVerilog/UVM
Job in
San Marcos, Hays County, Texas, 78667, USA
Listed on 2026-01-28
Listing for:
Mogi I/O : OTT/Podcast/Short Video Apps for you
Full Time
position Listed on 2026-01-28
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Test Engineer
Job Description & How to Apply Below
Location: USA - Texas Austin
Employment Type:
Permanent
Experience
Required:
5 - 10 Years (Minimum 3 years in Design Verification)
Compensation: USD 160000 - 180000
Position OverviewThe Verification Engineer will lead RTL design verification for high-speed digital systems. This role focuses on building verification environments, executing test strategies, and ensuring full functional coverage while collaborating with design and architecture teams.
Key Responsibilities- Develop and execute verification plans based on design specs
- Build and maintain SV/UVM environments
- Define and close functional and code coverage
- Debug RTL and support regression testing
- Participate in reviews, test planning, and sign-off
- Document results and collaborate cross-functionally
- 5+ years in digital/RTL engineering
- 3+ years in design verification
- Strong knowledge of VLSI verification flows
- Hands-on with System Verilog & UVM (or equivalent)
- Strong debugging and problem-solving skills
- Protocol/datapath verification experience (Ethernet preferred)
- Mixed-signal exposure
- Strong documentation and communication skills
Position Requirements
10+ Years
work experience
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