Member of Technical Staff, Hardware Systems & EDA

We are hiring one Member of Technical Staff to work at the intersection of digital hardware engineering, electronic design automation, and AI research. This is a full-time position based in San Mateo, California.

The core of this role is RTL design, FPGA implementation, verification, and EDA tooling. You will build working hardware systems and the automated workflows that let researchers and AI agents propose changes, test them, and measure whether they are actually better.

We are looking for an engineer who can own the path from specification and architecture through implementation, verification, and measured results. You should be comfortable challenging an evaluation setup, diagnosing a timing or correctness failure, and improving the tools themselves. Firmware, drivers, and experience across the hardware/software boundary are valuable complementary strengths.

• Design and implement digital hardware in Verilog or System Verilog, making explicit trade-offs between functionality, performance, power, area, and implementation complexity.
• Own verification strategies, including test benches, assertions, reference models, regression suites, and coverage. Turn an ambiguous specification into concrete checks for correctness.
• Take designs through simulation, synthesis, implementation, and timing analysis; validate behavior on FPGA hardware where appropriate and investigate differences between simulation and measured results.
• Build reproducible EDA workflows for design-space exploration, parameter sweeps, tool execution, artifact collection, and comparison against trusted baselines.
• Develop evaluation environments for AI-assisted hardware engineering with clearly specified tasks, fixed constraints, and checks that distinguish real improvements from invalid or incomplete solutions.
• Diagnose failures across RTL, verification infrastructure, timing constraints, EDA tools, and hardware interfaces. Improve the underlying implementation rather than relying on fragile workarounds.
• Own technical direction and implementation for substantial projects, working with researchers and systems engineers to make hardware experiments repeatable and results easy to inspect.

• Evidence of independently delivering a substantial digital hardware design or EDA system. You can explain the specification, architecture, verification strategy, implementation constraints, and results you personally owned.
• Strong RTL design skills in Verilog or System Verilog, including synchronous design, pipelining, finite-state machines, clock/reset design, and clock-domain crossing.
• Deep verification skills: self-checking test benches, assertions, corner-case analysis, reference models, and coverage-driven debugging. You understand why passing a simulation is not by itself evidence of correctness.
• Practical experience taking an RTL design through synthesis and implementation, reading timing and utilization reports, writing constraints, and closing timing on FPGA or ASIC flows.
• A strong understanding of computer architecture, memory systems, interconnects, and hardware interfaces, with the ability to reason quantitatively about latency, throughput, and resource use.
• Strong Python and working C or C++ skills for tool development, automation, reference models, and performance analysis. You can navigate unfamiliar codebases and extend existing engineering tools.
• A disciplined approach to experimentation: reproducible tool versions and configurations, controlled baselines, traceable artifacts, and careful interpretation of power, performance, and area results.
• The ability to define a technical plan from an open-ended problem, make defensible design decisions, and deliver with limited oversight. Clear specifications, design…