Lead Design Verification Architect; SystemVerilog​/UVM

Renesas Electronics is seeking a Principal Design Verification Engineer to lead verification for next‑generation memory interface products, including data buffers. You will define verification strategies, build reusable System Verilog/UVM environments, and guide teams to deliver robust designs.

The ideal candidate has deep semiconductor verification experience, expert System Verilog skills, and strong ownership of complex verification tasks, with a track record of driving coverage closure and

This posting is for the Lead Design Verification Architect (System Verilog/UVM) role at Renesas Electronics Corp., based in GA, United States.

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We are looking to fill the Lead Design Verification Architect (System Verilog/UVM) position at Renesas Electronics Corp. in GA, United States.