FPGA Verification Engineer

FPGA Verification Engineer

Location:

Santa Clara, CA (Onsite from Day
1)

Employment type:

Contract

• Develop and execute comprehensive verification plans for FPGA designs.
• Create and maintain test benches using industry‑standard verification methodologies (e.g., UVM, System Verilog).
• Write and debug test cases to verify functionality, performance, and corner cases.
• Perform code coverage and functional coverage analysis.
• Identify and debug issues, working closely with design engineers to resolve them.
• Document verification results and provide clear and concise reports.

• Strong understanding of FPGA design principles and architectures.
• Proficiency in System Verilog and UVM verification methodology.
• Experience with industry‑standard verification tools (e.g., Questa Sim, Synopsys VCS).
• Knowledge of code coverage and functional coverage analysis.

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of experience in FPGA verification.
• Experience with scripting languages (e.g., Python, Perl).
• Familiarity with hardware description languages (e.g., VHDL, Verilog).

Mid-Senior level

Contract

Quality Assurance

IT Services and IT Consulting