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Hybrid Mixed-Signal Model Verifier; SystemVerilog​/Analog

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: Dexian DISYS
Full Time position
Listed on 2025-12-08
Job specializations:
  • Engineering
    Systems Engineer
Salary/Wage Range or Industry Benchmark: 90 - 95 USD Hourly USD 90.00 95.00 HOUR
Job Description & How to Apply Below
Position: Hybrid Mixed-Signal Model Verifier (SystemVerilog/Analog)
A leading technology solutions firm in California seeks a Mixed Signal Model Verification Engineer for a hybrid role. The ideal candidate will verify System Verilog behavioral models against analog circuit schematics and have extensive experience in real number modeling and HDL/SPICE co-simulations.

Experience with formal equivalence checking tools is essential. This contract position offers competitive compensation of $90-95/hr for a duration of 3+ months.
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