Modeling​/Verification Engineer - Intermediate

Preference is Hybrid but Open to a fully remote candidate.

Interview: 1hr long interview with Sr. Engineer in India.

• Minimum 5 years of experience in System
  
  C.
• Recent and relevant experience with System
  
  C.
• Resume includes hands‑on modeling projects using System
  
  C.
• Familiarity with Transaction‑Level Modeling (TLM) concepts and implementation.
• Experience in performance modeling and architecture exploration using System
  
  C.
• Ability to work with C++ integration, since System
  
  C is built on C++.
• Exposure to verification methodologies in System
  
  C (e.g., testbench creation, simulation).
• Knowledge of modeling at different abstraction levels (e.g., behavioral, RTL, TLM).

• Develop, enhance, and maintain System
  
  C/TLM2 models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware.
• Collaborate with cross teams to integrate models into AMD tools used for system‑level designs, ensuring proper functionality and performance.
• Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications.
• Develop and execute test benches to validate the functionality and correctness of models, as well as participate in system‑level testing and debugging.
• Create clear and comprehensive documentation for models, including usage guidelines and design specifications.

• Cycle approximate performance models
• SV/UVM Functional and Performance Verification

• B.E/M.E/M.Tech or
  
  B.S/M.S in EE/CSE with over 5 years of recent hands‑on experience in System
  
  C and TLM2 modeling
• Proficiency in C/C++ programming.
• Understanding of memory controller architectures, including DDR, LPDDR, and other relevant standards is preferred.
• UVM verification experience is preferred.
• Experience with debuggers and handling complex projects.
• Experience working in geographically dispersed teams; must be a strong team player.
• Knowledge of system‑level architecture including buses like AXI/AHB and bridges is a plus.
• Familiarity with version control systems such as Perforce or Git.