Senior ASIC RTL Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

As a member of the AMD front‑end design/integration team, you will help bring to life cutting‑edge designs and deliver IPs to SOC. You will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first‑pass silicon success.

You have a passion for modern, complex processor architecture, digital design, and verification/design quality. You are a team player with excellent communication skills, strong analytical and problem‑solving skills, and a willingness to learn and take on challenges. A global mindset and the ability to work in a multi‑site environment are keys to success in this role.

• RTL design of high‑speed designs, clock/reset/power features, IP integration, sub‑system level design
• Architect and design of power management features
• Design optimization for implementing power‑efficient IP, implementing RTL using low‑power techniques
• Resolve inter‑IP integration issues
• Own clock‑domain crossing, linting aspects of the overall design of the IP and subsystem
• Work closely with FEINT, DFT, Physical Design and SOC teams to incorporate interdisciplinary feedback into the design
• Architect, micro‑architect, and document design features
• Demonstrate commitment to innovation as a team through excellent communication, documentation, and independent task completion

• Extensive experience in digital IP/ASIC design and Verilog RTL development
• Experience in full IP design cycle: requirements definition, architecture, and micro‑architecture specification
• Well versed in RTL design verification, design quality checks, synthesis, timing closure, and post‑silicon validation
• Expert in Verilog RTL design with experience in multi‑scale digital IP/ASIC projects; experience with front‑end EDA tools sign‑off and its flows
• Familiarity with low power design and low power flow is a plus
• Programming with scripting languages such as Python or Perl is a plus
• Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements
• Proven interpersonal skills, leadership and teamwork
• Excellent writing skills in English, editing and organizational skills; skilled at prioritization and multi‑tasking
• Good understanding of engineering terminology used within the semiconductor industry; good understanding of digital design concepts
• Knowledge or experience in functional design verification or design is highly desired

• Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering

This role is not eligible for visa sponsorship.

LOCATION:
Santa Clara, CA

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.