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Physical Design Manager

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: Bayasystems
Full Time position
Listed on 2025-12-31
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 150000 - 200000 USD Yearly USD 150000.00 200000.00 YEAR
Job Description & How to Apply Below

Direct message the job poster from Baya Systems

Job Title

Physical Design Engineer Team Lead

About the Role

We are seeking a seasoned Physical Design Engineer/Team Lead with a strong background in all aspects of Physical Design and Implementation flows. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Responsibilities
  • Own RTL to GDS physical implementation flows for synthesis, floor-planning, place and route, clock tree synthesis, timing & power closure, EM/IR, PDV and final PD sign off
  • Own physical design & implementation of high-performance designs from block level to system level components
  • Deep collaboration with Micro-architects to explore performance, power and area trade-offs for high performance and low power designs
  • Physical implementation feasibility studies and design recommendations for best PPA
  • Develop methodologies and recipes for various stages of physical implementation
  • Perform design rule checking (DRC), (LVS) checks, and other physical verification tasks
Qualifications
  • BS, MS in Electrical Engineering or Computer Engineering or related degree
  • Experience in all aspects of physical design including synthesis, floor planning, place & route, timing & power closure, EM/IR, physical design validation, etc
  • Experience with synthesis, place & route, static timing analysis and PDV tools
  • Experience in implementing clock trees and power grids
  • Experience with scripting for physical design flow automation
  • Experience with Synopsys Design Compiler, Prime Time, ICC, Fusion Compiler etc.
  • Good knowledge of high-performance and low-power microarchitecture and logic design principles
  • Understanding of modern (sub 7nm) sub-micron technology nodes and device physics
  • Basic knowledge of System/SoC Architecture and System Verilog RTL coding
  • Strong communication and collaboration skills
Seniority Level

Director

Employment Type

Full-time

Job Function

Semiconductor Manufacturing, Computer Hardware Manufacturing, and Software Development

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