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Senior ASIC RTL Verification Engineer – DDR/UVM; Hybrid
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-01-01
Listing for:
Tech Providers,
Full Time
position Listed on 2026-01-01
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
A leading tech solutions company in California is seeking a Design Verification Engineer with a minimum of 8 years of design verification experience. The role involves developing and maintaining functional verification tests, collaborating with various engineering teams, and debugging design defects. Candidates should possess strong skills in System Verilog and have a passion for complex processor architecture. This hybrid position offers flexibility with remote options, preferably within the PST timezone.
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Position Requirements
10+ Years
work experience
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