Senior Digital Verification Engineer - SystemVerilog​/UVM

A growing technology firm in California is seeking a skilled verification engineer with a Bachelor’s degree in electrical or computer engineering and 3–5+ years of hands-on experience. The role focuses on building cutting-edge verification environments, collaborating with teams, and developing comprehensive test plans. Proficiency in System Verilog, UVM, and strong communication skills are essential. Competitive salary ranging from $70,000 to $90,000 USD is offered.
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