SOC Design Verification Engineer

We are seeking an experienced SoC Design Verification Engineer with a strong background in UVM-based verification and System Verilog to join our dynamic engineering team. The ideal candidate will have hands‑on experience in developing and executing complex verification environments, integrating C/C++ models, and debugging issues at both IP and subsystem levels.

Develop, implement, and maintain UVM-based verification environments for SoC and IP-level designs.

Write and execute System Verilog assertions to validate design functionality and performance.

Integrate C/C++ reference models within verification test benches and ensure co‑simulation.

Perform debugging at IP and subsystem levels
, identifying and resolving functional and timing issues.

Collaborate with design, architecture, and validation teams to define verification plans, strategies, and coverage goals.

Review and analyze waveforms, simulation logs, and coverage reports to ensure thorough verification closure.

Participate in regression management, bug tracking, and documentation for design verification deliverables.

Bachelor’s or Master’s degree inb>

Electrical Engineering Computer Engineering, or related field.

10+ years of hands‑on experience in SoC or IP-level design verification
.

Strong proficiency in System Verilog
, UVM methodology
, and assertion-based verification (ABV).

Proven debugging skills at both IP and subsystem levels using industry‑standard EDA tools (e.g., Synopsys VCS, Cadence Xcelium, or Mentor Questa).

Gate-Level Simulation (GLS) and post‑silicon verification exposure.

Experience with Low Power Verification (UPF / CPF) methodologies.

Familiarity with ARM-based So architectures and interconnect verification.

$160,000 - $180,000 USD