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Analog Mixed Signal Design Engineer

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: EnCharge AI
Full Time position
Listed on 2026-01-04
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
Analog Mixed Signal Design Engineer at EnCharge AI

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders‑of‑magnitude higher compute efficiency and density compared to today’s best‑in‑class solutions. The high‑performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications.

EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

About

The Role

We are seeking an Analog Mixed Signal Design Engineer. This role will drive the development of state‑of‑the‑art analog IP and SoCs to meet aggressive power, performance, and area targets. The individual will contribute to the design of a wide range of analog and mixed‑signal circuits, including switched‑capacitor circuits, ADCs, DACs, memory, and amplifiers.

The successful candidate will participate in all phases of the design lifecycle, including architecture and specification definition, circuit design and simulation, layout and layout supervision, chip verification, and prototype evaluation. This role also requires coordinating and overseeing test efforts in both laboratory and production test environments.

Qualifications

• BS/MS/PhD in Electrical Engineering or related field with coursework, projects and/or experience in analog / mixed signal design.

• One or more of the following work experience is required for this role:
- Experience in design of switched capacitor circuits (ADCs, DACs) etc.
- Experience in the design of SAR ADCs

- Experience with design and testing of integrated DCDC converters (Buck)

- Experience with analog circuit design from scratch (spec level)
- Experience in advanced CMOS technology nodes (16nm and below)
- Experience in System Verilog / Veriloga modeling of analog circuits

- Experience with Post‑Silicon lab bring up, evaluation and debug

• Ability to supervise layout resources in layout critical designs

• Familiarity with the latest analog and mixed‑signal design tools and simulation techniques

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