FPGA Verification Engineer | UVM​/SystemVerilog Expert

A leading engineering company is seeking a highly skilled FPGA Verification Engineer in Santa Clara, CA. You will verify complex FPGA designs, collaborating closely with design engineers and ensuring product quality. The ideal candidate will have over 8 years of experience in FPGA and strong proficiency in UVM and System Verilog. This is a full-time onsite role, requiring a Bachelor's or Master's degree in Electrical or Computer Engineering.

Competitive rate offered with 5 days onsite per week.
Join us at Allps GmbH as our next FPGA Verification Engineer | UVM/System Verilog Expert in Santa Clara, CA, United States. We are currently recruiting a FPGA Verification Engineer | UVM/System Verilog Expert for our team in Santa Clara, CA, United States. This is a genuine role to take on the FPGA Verification Engineer | UVM/System Verilog Expert role at Allps GmbH.