Lead, HBM Memory Subsystem Validation
Listed on 2026-10-07
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Engineering
Test Engineer, Validation Engineer
AMD in Santa Clara, CA is seeking a Memory Sub-system Validation Lead to drive pre- and post-silicon validation of on-die HBM for the Datacenter GPU line. You will partner with DRAM, Memory Controller, DV, DDR PHY, DRAM product engineering and software teams to ensure memory designs meet quality standards.
As a hands-on leader, you will mentor engineers, develop test plans, and lead by example in a lab environment, delivering thorough validation results and clear defects to mass production.
This is an excellent opening to take on the Lead, HBM Memory Subsystem Validation role at Advanced Micro Devices.
The advertised compensation is 170..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Lead, HBM Memory Subsystem Validation role in the description above.
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