Senior ASIC Emulation Engineer

At Palo Alto Networks®, we’re united by a shared mission—to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting‑edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you’re ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you’re in the right place.

In order to be the cybersecurity partner of choice, we must trailblaze the path and shape the future of our industry. This is something our employees work at each day and is defined by our values:
Disruption, Collaboration, Execution, Integrity, and Inclusion. We weave AI into the fabric of everything we do and use it to augment the impact every individual can have. If you are passionate about solving real‑world problems and ideating beside the best and the brightest, we invite you to join us!

We believe collaboration thrives in person. That’s why most of our teams work from the office full time, with flexibility when it’s needed. This model supports real‑time problem‑solving, stronger relationships, and the kind of precision that drives great outcomes.

As a Senior/Lead ASIC Emulation Engineer on the ASIC team, you will drive the execution, verification, and validation of high‑complexity network security processors and compute architectures on state‑of‑the‑art emulation and FPGA prototyping platforms. In this role, you will bridge the gap between pre‑silicon hardware design, firmware/software development, and post‑silicon validation. You will define emulation architecture, build scalable hybrid co‑emulation environments, accelerate pre‑silicon software bring‑up, and ensure our next‑generation firewall products achieve industry‑leading performance and reliability.

We expect office‑based employees to be in the office four days per week, with one day working from where they choose. We believe being together facilitates casual conversations and those magic moments where we can work on issues and ideas informally. These moments build capability and deepen trusted relationships and allow our people to feel safe in taking risks and being disruptive.

• Architect, bring up, and maintain enterprise‑scale hardware emulation platforms (e.g., Palladium, ZeBu, Veloce) and hybrid co‑emulation/virtual prototyping systems.
• Collaborate closely with ASIC Architecture, Design, Verification, and Software/Firmware teams to define pre‑silicon emulation plans and execution timelines.
• Compile, synthesize, and fit multi‑million/billion‑gate SoC designs onto emulation hardware, performing power, timing, and capacity optimization.
• Develop and maintain transactors, rate adapters, speed adapters, and hybrid virtual interfaces (C/C++, SystemC, DPI) to connect emulation models with host software test benches and real‑world network traffic generators.
• Enable pre‑silicon software development and OS/driver bring‑up by executing real‑world workloads, benchmarks, and regression suites on the emulator.
• Debug complex, deep‑trace hardware, firmware, and protocol‑level failures using advanced emulation debug features (waveform captures, readback, dynamic probes, assertions).
• Automate build, deployment, triage, and regression flows using Python, Tcl, and CI/CD pipelines to optimize model compile speed and platform utilization.
• Partner with post‑silicon validation teams to reproduce and triage silicon anomalies on the emulation platform.

Qualifications

• Education: BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• Core
  
  Experience:
  
  8+ years of hands‑on experience in hardware emulation, FPGA…