DFT​/DFx Architecture & RTL Lead

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward.

Join us and, together, we’ll advance your career.

THE ROLE:

The Circuit Technology team is looking for an experienced DFT/DFx Methodology, Architecture, and RTL Execution Lead to support high-speed Ser Des PHYs, next-generation Memory PHYs, and die-to-die interconnect  this role, you will own and lead DFT/DFx architecture definition, RTL implementation, methodology development, scan integration support, test constraints, ATPG support, and post-silicon debug for advanced PHY and connectivity IP designs. You will collaborate closely with design, verification, physical design, CAD, product engineering, and test engineering teams to deliver robust, high-coverage, production-ready  part of a collaborative team delivering advanced IP used across SoCs.THE

PERSON:

The successful candidate brings analytical and problem-solving skills, attention to technical quality, and the ability to lead complex technical work with appropriate autonomy and cross-functional collaboration. The candidate should be able to contribute directly to technical implementation while providing technical leadership across architecture, methodology, RTL implementation, verification, and silicon debug.

KEY RESPONSIBILITIES:

Define and lead PHY-specific DFT/DFx architecture and methodology for high-speed Ser Des, Memory PHY, and die-to-die interconnect IPs.Implement DFT/DFx features in RTL using Verilog/System Verilog.

Develop and support DFT micro-architecture, including scan architecture, test modes, clocking, reset, isolation, bypass, and observability features.

Support JTAG/IJTAG, ICL/PDL, scan compression, at-speed scan, and hierarchical DFT implementation.

Support Siemens Tessent-based or equivalent industry-standard DFT flows for ATPG, pattern generation, pattern validation, and debug.

Support scan stitching, scan-readiness checks, test coverage analysis, and DFT rule/debug closure.

Develop and maintain DFT timing constraints, test-mode constraints, and integration guidelines compatible with front-end and physical design flows.

Perform gate-level simulation and debug using tools such as Synopsys VCS and Verdi or comparable tools.

Drive Spy Glass or equivalent lint/DFT-readiness analysis to identify scan, cont rollability, observability, and test coverage gaps.

Plan, implement, and verify MBIST-related features for embedded memories.

Support ATPG pattern generation, simulation, debug, and delivery to test engineering.

Partner with Test Engineering and Product Engineering on silicon bring-up, tester pattern debug, diagnosis, and yield-learning activities.

Develop efficient and reusable DFx flows, scripts, checkers, and methodologies for IP-level and SoC-level integration.

PREFERRED EXPERIENCE:

Relevant industry experience in DFT, DFx, RTL design, semiconductor IP development, or SoC test methodology. Level will be determined based on demonstrated technical scope, relevant experience, and role-related interview criteria.

Understanding of DFT architecture and micro-architectures, including scan, compression, test clocks, test resets, lock-up latches, clock gates, scan anchors, and test access mechanisms.

Hands-on experience with Siemens Tessent DFT flows, such as Tessent Shell, Tessent Scan, Tessent ATPG, Tessent Test Kompress, Tessent MemoryBIST, IJTAG, ICL/PDL, and/or Streaming Scan Network/SSN, or experience with comparable industry-standard DFT tools and methodologies.

Experience developing or supporting hierarchical DFT flows for complex SoCs or reusable IPs.Hands-on RTL coding experience in Verilog and/or System Verilog.

Experience with industry-standard ATPG, scan insertion, and DFT implementation tools.

Familiarity with JTAG, IJTAG, ICL/PDL, scan compression, at-speed scan, and hierarchical DFT concepts.

Experience with gate-level simulation, debug, and waveform analysis using tools such as Synopsys VCS and Verdi or comparable technologies.

Experience analyzing DFT readiness, lint, cont rollability, observability, and test coverage issues.

Understanding of MBIST planning,…