Hardware Engineer, AI Accelerator Module Design

The Hardware Design, Rack-scale Technology and Platforms (HDRTP) engineering team designs, develops, validates, and delivers the hardware platforms that power Meta's AI and HPC infrastructure, deployed in data centers worldwide. Our designs are published for industry adoption through the Open Compute Project Foundation.

We are seeking a senior AI Accelerator Module Design Engineer to serve as the technical owner for the electrical and PCB design of accelerator modules supporting Meta's custom silicon (MTIA) and third-party AI accelerators. This is a lead individual-contributor role: you will own module-level electrical architecture end to end from requirements definition and ASIC package-to-board co-design through schematic, stackup, power delivery, bring-up, and volume production across multiple concurrent programs and silicon generations.

You will define the design methodologies, reference architectures, and design-rule standards that other engineers and ODM partners build against; resolve the hardest cross-domain trade-offs between signal integrity, power integrity, thermal, mechanical, and cost; and influence ASIC and rack-level architecture decisions upstream of the module. You will operate with minimal direction in an ambiguous, fast-moving environment, and will mentor and raise the technical bar for PCB and module engineers across the team.

Hardware Engineer, AI Accelerator Module Design Responsibilities:

Own the end-to-end electrical architecture and PCB design of AI accelerator modules for high-performance, high-power, high-efficiency custom silicon (MTIA) and third-party accelerators

Define module requirements and specifications in partnership with ASIC, platform, rack, and systems architecture teams translate system-level targets into implementable board-level design intent

Lead ASIC package-to-board co-design, including breakout routing strategy, substrate and interposer interaction, and escape feasibility analysis for high pin-count, high-bandwidth devices

Architect power delivery networks for extreme-current loads (multi-hundred-amp rails), owning DC-DC topology and architecture trade-offs (performance, transient response, efficiency, area, cost), decoupling strategy, and plane/stackup partitioning

Drive high-speed interface design across PCIe Gen5/Gen6, CXL, UCIe, DDR5/LPDDR, HBM, NVLink/scale-up fabrics, and Ethernet up to 800G, including simulation-guided stackup and channel budgeting

Set the technical direction for SI/PI methodology in partnership with Signal and Power Integrity teams define correlation strategy between simulation and measured silicon

Define and own module-level design reviews set the quality bar for schematic, layout, and DFM/DFT readiness across internal designs and ODM-executed designs

Lead board and silicon bring-up and own root-cause analysis of the most complex electrical, power, and interoperability failures drive corrective design action to closure

Drive ODM/JDM partners through full NPI-to-mass-production cycles, holding partners to Meta design standards and schedule

Develop reusable reference designs, design-rule libraries, and design automation that scale across programs and generations publish and champion designs through the Open Compute Project Evaluate and qualify leading-edge technologies with industry partners — HDI and advanced substrates, embedded components, novel materials, co-packaged and coherent optics — and build the business case for adoption

Identify cross-organizational problems and lead XFN efforts to resolution without being asked influence decisions outside your direct scope through technical credibility rather than authority

Mentor and develop PCB/module design engineers contribute to hiring, calibration of technical standards, and…