Physical Design Engineer

At SK hynix memory solutions,we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in NAND flash technology and memory solutions, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting‑edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK hynix memory solutions, you will be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco‑friendly solutions and operational practices.

As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

About the Role

Join our Physical Design (SoC Integration) team responsible for delivering high-performance SoC designs from RTL to GDS. As a Sr. Staff Physical Design Engineer, you will lead physical implementation efforts for advanced-node designs, driving critical blocks through synthesis, placement, CTS, routing, and signoff. You will work closely with front-end, DFT, power, and analog teams to optimize PPA (Power, Performance, Area) while ensuring silicon success.

This role requires deep hands‑on expertise across the full physical design flow as well as leadership to mentor junior engineers and define methodologies for the team.

Responsibilities

• Lead physical design implementation from synthesis through GDS for high-performance blocks or full-chip SoC designs in advanced process nodes (7nm, 5nm, 3nm)
• Execute and optimize synthesis, placement, clock tree synthesis (CTS), and routing using industry-standard P&R tools (Synopsys ICC2/Fusion Compiler or Cadence Innovus)
• Drive timing closure and signoff using Prime Time (PT), including advanced analysis such as SI, AOCV/POCV, crosstalk, and ECO implementation
• Perform RC extraction using StarRC or Quantus and ensure strong correlation between extraction and STA results
• Own physical verification signoff with Mentor/Siemens Calibre, resolving DRC, LVS, ERC, and antenna violations in complex FinFET layouts
• Conduct power integrity analysis using Ansys Red Hawk(Redhawk-SC), including static/dynamic IR drop and EM analysis; implement power grid and decap optimizations
• Develop and maintain physical design flows and automation scripts (Tcl, Perl, Python), mentor junior engineers, and collaborate with cross-functional teams to achieve tapeout schedules

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field (Master's preferred)
• 6+ years of hands‑on experience in ASIC physical design with proven tapeout success
• Expert-level proficiency in synthesis, placement, CTS, and routing using Synopsys or Cadence P&R tools
• Deep knowledge of static timing analysis (STA) and Prime Time signoff, including multi‑corner/multi‑mode closure
• Demonstrated experience with physical verification using Calibre (DRC, LVS, ERC) and IR drop/EM analysis using Red Hawk

Preferred Qualifications

• Experience at 5nm or 3nm process nodes with FinFET and multi-patterning design rules
• Familiarity with low-power design techniques including UPF, clock gating, multi‑Vt, and voltage islands
• Strong programming skills in…